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? 2004 microchip technology inc. ds21140f-page 1 24lc41 features ? single supply with operation down to 2.5v completely implements ddc1 ? /ddc2 ? interface for monitor identification separate high speed 2-wire bus for microcontroller access to 4k-bit serial eeprom low-power cmos technology 2 ma active current typical 20 a standby current typical at 5.5v dual 2-wire serial interface bus hardware write-protect for both ports self-timed write cycle (including auto-erase) page write buffer for up to 8 bytes (ddc port) or 16 bytes (4k port) 100 khz (2.5v) and 400 khz (5v) compatibility 1,000,000 erase/write cycles ensured data retention > 40 years 8-pin pdip package available for extended temperature ranges description the microchip technology inc. 24lc41 is a dual-port 128 x 8 and 512 x 8-bit electrically erasable prom (eeprom). this device is designed for use in applica- tions requiring storage and serial transmission of configuration and control information. three modes of operation have been implemented: transmit-only mode for the ddc monitor port bidirectional mode for the ddc monitor port bidirectional, industry-standard 2-wire bus for the 4k microcontroller access port upon power-up, the ddc monitor port will be in the transmit-only mode, repeatedly sending a serial bit stream of the entire memory array contents, clocked by the vclk/dwp pin. a valid high-to-low transition on the dscl pin will cause the device to enter the bidirec- tional mode, with byte-selectable read/write capability of the memory array. the 4k-bit microcontroller port is completely independent of the ddc port, therefore, it can be accessed continuously by a microcontroller without interrupting ddc transmission activity. the 24lc41 is available in a standard 8-pin pdip package in both commercial and industrial temperature ranges. package type block diagram - commercial (c): 0c to +70c - industrial (i): -40c to +85c 24lc41 dscl vclk/dwp v ss msda 1 2 3 4 8 7 6 5 dsda v cc mwp mscl pdip edid table 1k bit 4k bit serial eeprom msda mscl mwp dsda vclk/dwp dscl ddc monitor port microcontroller access port 1k/4k 2.5v dual mode, dual port i 2 c ? serial eeprom obsolete device i 2 c is a registered trademark of philips corporation.
24lc41 ds21140f-page 2 ? 2004 microchip technology inc. 1.0 electrical characteristics 1.1 absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................7.0v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-65c to +125c esd protection on all pins ............................................................................................................................... ....................... 4 kv table 1-1: dc characteristics ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics v cc = +2.5v to 5.5v commercial (c): t a = 0c to +70c industrial (i): t a = -40c to +85c parameter symbol min max units conditions dscl, dsda, mscl & msda pins: high-level input voltage low-level input voltage v ih v il .7 v cc ? ? .3 v cc v v input levels on vclk/dwp pin: high-level input voltage low-level input voltage v ih v il 2.0 ? .8 .2 v cc v v v cc 2.7v (note) v cc < 2.7v (note) hysteresis of schmitt trigger inputs v hys .05 v cc ?v (note) low-level output voltage v ol 1 ?.4vi ol = 3 ma, v cc = 2.5v (note) low-level output voltage v ol 2 ?.6vi ol = 6 ma, v cc = 2.5v input leakage current i li ?1 av in = .1v to v cc output leakage current i lo ?1 av out = .1v to v cc pin capacitance (all inputs/outputs) c in , c out ?10pfv cc = 5.0v (note) , t a = 25 c, f clk = 1 mhz operating current i cc write i cc read ? ? 3 1 ma ma v cc = 5.5v, dscl or mscl = 400 khz standby current i ccs ? ? 60 200 a a v cc = 3.0v, dsda or msda = dscl or mscl = v cc v cc = 5.5v, dsda or msda = dscl or mscl = v cc v clk = v ss note: this parameter is periodically sampled and not 100% tested.
? 2004 microchip technology inc. ds21140f-page 3 24lc41 table 1-2: ac characteristics ( ddc monitor and microcontroller access ports) ddc monitor port (bidirectional mode) and microcontroller access port parameter symbol standard mode vcc = 4.5 - 5.5v fast mode units remarks min max min max clock frequency (dscl and mscl) f clk ? 100 ? 400 khz clock high time (dscl and mscl) t high 4000 ? 600 ? ns clock low time (dscl and mscl) t low 4700 ? 1300 ? ns dscl, dsda, mscl and msda rise time t r ? 1000 ? 300 ns (note 1) dscl, dsda, mscl and msda fall time t f ? 300 ? 300 ns (note 1) start condition hold time t hd : sta 4000 ? 600 ? ns after this period the first clock pulse is generated start condition setup time t su : sta 4700 ? 600 ? ns only relevant for repeated start condition data input hold time t hd : dat 0?0?ns (note 2) data input setup time t su : dat 250 ? 100 ? ns stop condition setup time t su : sto 4000 ? 600 ? ns output valid from clock t aa ? 3500 ? 900 ns (note 2) bus free time t buf 4700 ? 1300 ? ns time the bus must be free before a new transmission can start output fall time from v ih min to v il max t of ? 250 20 + .1 c b 250 ns (note 1) , c b 100 pf input filter spike suppression (dscl, dsda, mscl and msda pins) t sp ?50?50ns (note 3) write cycle time t wr ? 10 ? 10 ms byte or page mode ddc monitor port transmit-only mode parameters output valid from vclk/ dwp t vaa ? 2000 ? 1000 ns vclk/dwp high time t vhigh 4000 ? 600 ? ns vclk/dwp low time t vlow 4700 ? 1300 ? ns mode transition time t vhz ? 500 ? 500 ns transmit-only power-up time t vpu 0?0?ns endurance ? 1m ? 1m ? cycles 25c, vcc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of dscl or mscl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise and spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from our web site.
24lc41 ds21140f-page 4 ? 2004 microchip technology inc. 2.0 functional description 2.1 ddc monitor port the ddc monitor port operates in two modes, the transmit-only mode and the bidirectional mode. there is a separate 2-wire protocol to support each mode, each having a separate clock input and sharing a common data line (dsda). the device enters the transmit-only mode upon power-up. in this mode, the device transmits data bits on the dsda pin in response to a clock signal on the vclk/dwp pin. the device will remain in this mode until a valid high-to-low transition is placed on the dscl input. when a valid transition on dscl is recognized, the device will switch into the bidirectional mode. the only way to switch the device back to the transmit-only mode is to remove power from the device. 2.2 transmit-only mode the device will power-up in the transmit-only mode. this mode supports a unidirectional 2-wire protocol for transmission of the contents of the memory array. this device requires that it be initialized prior to valid data being sent in the transmit-only mode ( section 2.3 ?initialization procedure? ). in this mode, data is transmitted on the dsda pin in 8-bit bytes, each followed by a ninth, null bit (figure 2-1). the clock source for the transmit-only mode is provided on the vclk/dwp pin, and a data bit is output on the rising edge on this pin. the eight bits in each byte are trans- mitted by most significant bit first. each byte within the memory array will be output in sequence. when the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. the bidirectional mode clock (dscl) pin must be held high for the device to remain in the transmit-only mode. 2.3 initialization procedure after v cc has stabilized, the device will be in the transmit-only mode. nine clock cycles on the vclk/ dwp pin must be given to the device for it to perform internal sychronization. during this period, the dsda pin will be in a high-impedance state. on the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit of a byte. the device will power-up at an indeterminate byte address (figure 2-2). figure 2-1: transmit-only mode figure 2-2: device initialization dscl dsda vclk/dwp t vaa t vaa bit 1 (lsb) null bit bit 1 (msb) bit 7 t vlow t vhigh t vaa t vaa bit 8 bit 7 high-impedance for 9 clock cycles t vpu 12 891011 scl sda vclk/dwp v cc
? 2004 microchip technology inc. ds21140f-page 5 24lc41 2.3.1 bidirectional mode the ddc monitor port can be switched into the bidirectional mode (figure 2-3) by applying a valid high-to-low transition on the bidirectional mode clock (dscl). when the device has been switched into the bidirectional mode, the vclk/dwp input is disre- garded, with the exception that a logic high level is required to enable write capability. this mode supports a 2-wire bidirectional data transmission protocol. in this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. the bus must be controlled by a master device that generates the bidirectional mode clock (dscl), controls access to the bus and generates the start and stop conditions, while the ddc monitor port acts as the slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 2.4 microcontroller access port the microcontroller access port supports a bidirec- tional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (mscl), controls the bus access, and generates the start and stop conditions, while the microcontroller access port works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. figure 2-3: mode transition dscl dsda vclk/dwp bidirectional mode t vhz transmit-only mode
24lc41 ds21140f-page 6 ? 2004 microchip technology inc. 3.0 bidirectional bus characteristics characteristics for the bidirectional bus are identical for both the ddc monitor port (in bidirectional mode) and the microcontroller access port the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high-to-low transition of the dsda or msda line while the clock (dscl or mscl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low-to-high transition of the dsda or msda line while the clock (dscl or mscl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. when an overwrite does occur, it will replace data in a first in first out fashion. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the dsda or msda line during the acknowledge clock pulse in such a way that the dsda or msda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowl- edge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. 3.6 device addressing a control byte is the first byte received following the start condition from the master device. the first part of the control byte consists of a 4-bit control code. this control code is set as 1010 for both read and write oper- ations and is the same for both the ddc monitor port and microcontroller access port. the next three bits of the control byte are block select bits (b1, b2 and b0). all three of these bits are don?t care bits for the ddc monitor port. the b2 and b1 bits are don?t care bits for the microcontroller access port, and the b0 bit is used by the microcontroller access port to select which of the two 256 word blocks of memory are to be accessed (figure 3-4). the b0 bit is effectively the most signifi- cant bit of the word address. the last bit of the control byte defines the operation to be performed. when set to one, a read operation is selected; when set to zero, a write operation is selected. following the start condi- tion, the device monitors the dsda or msda bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the device will select a read or a write operation. the ddc monitor port and microcon- troller access port can be accessed simultaneously because they are completely independent of one another. note: the microcontroller access port and the ddc monitor port (in bidirectional mode) will not generate any acknowledge bits if an internal programming cycle is in progress. operation control code chip select r/w read 1010 xxb0 1 write 1010 xxb0 0
? 2004 microchip technology inc. ds21140f-page 7 24lc41 figure 3-1: data transfer sequence on the serial bus figure 3-2: bus timing start/stop figure 3-3: bus timing data figure 3-4: contro l byte allocation dscl dsda ( a )(b) (d) (d) (c)( a ) start condition address or acknowledge valid data allowed to change stop condition or mscl or msda mscl dsda t su : sta t hd : sta start stop v hys t su : sto or mscl in or msda in dscl dsda dsda t hd : sta t su : sta t f t high t r t su : sto t su : dat t hd : dat t buf t aa t hd : sta t aa t sp t low or mscl in or msda in or msda out x = don?t care. b0 is don?t care for ddc monitor port, but is us ed by the microcontroller access port to select which of the tw o 256 word blocks of memory are to be accessed. r/w a 1 010xxx read/write start slave address
24lc41 ds21140f-page 8 ? 2004 microchip technology inc. 4.0 write operation write operations are identical for the ddc monitor port (when in bidirectional mode) and the microcontroller access port, with the exception of the vclk/dwp and mwp pins noted in the next sections. data can be written using either a byte write or page write command. write commands for the ddc monitor port and the microcontroller access port are completely independent of one another. 4.1 byte write following the start signal from the master, the slave address (4-bits), the chip select bits (3-bits) and the r/w bit which is a logic low is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmit- ted by the master is the word address and will be written into the address pointer of the port. after receiving another acknowledge signal from the port, the master device will transmit the data word to be written into the addressed memory location. the port acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time, the port will not generate acknowledge signals (figure 4-1). for the ddc monitor port it is required that vclk/dwp be held at a logic high level in order to program the device. this applies to byte write and page write operation. note that vclk/dwp can go low while the device is in its self-timed program operation and not affect programming. for the microcontroller access port, the mwp pin must be held to v ss during the entire write operation. 4.2 page write the write control byte, word address, and the first data byte are transmitted to the port in the same way as in a byte write. but, instead of generating a stop condition, the master transmits up to eight data bytes to the ddc monitor port or 16 bytes to the microcontroller access port, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the higher order 5-bits of the word address remains constant. if the master should transmit more than eight words to the ddc monitor port or 16 words to the microcontroller access port prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an internal write cycle will begin (figure 4-2). for the ddc monitor port, it is required thatvclk/ dwp be held at a logic high level in order to program the device. this applies to byte write and page write operation. note that vclk/dwp can go low while the device is in its self-timed program operation and not affect programming. for the microcontroller access port, the mwp pin must be held to v ss during the entire write operation.. note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multi- ples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
? 2004 microchip technology inc. ds21140f-page 9 24lc41 figure 4-1: byte write figure 4-2: page write s p s t a r t s t o p bus activity master sda or bus activity a c k a c k a c k control byte word address data msda line vclk s p sda line s t a r t control byte word address data n data n + 15 s t o p a c k a c k a c k a c k a c k data n + 1 vclk/dwp bus activity master bus activity
24lc41 ds21140f-page 10 ? 2004 microchip technology inc. 5.0 acknowledge polling acknowledge polling can be done for both the ddc monitor port (when in bidirectional mode) and the microcontroller access port. since the port will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize but throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for the flow diagram. figure 5-1: acknowledge polling flow 6.0 write protection 6.1 ddc monitor port when using the ddc monitor port in the bidirectional mode, the vclk/dwp pin operates as the write-protect control pin. setting vclk/dwp high allows normal write operations, while setting vclk/dwp low prevents writing to any location in the array. connecting the vclk/dwp pin to v ss would allow the ddc moni- tor port to operate as a serial rom, although this configuration would prevent using the device in the transmit-only mode. 6.2 microcontroller access port the microcontroller access port can be used as a serial rom when the mwp pin is connected to v cc . programming will be inhibited and the entire memory associated with the microcontroller access port will be write-protected. send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes
? 2004 microchip technology inc. ds21140f-page 11 24lc41 7.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read and sequential read. these operations are identical for both the ddc monitor port (in bidirectional mode) and the microcontroller access port and are completely independent of one another. 7.1 current address read the port contains an address counter that maintains the address of the last word accessed, internally incre- mented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the port issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the port discontinues transmission (figure 7-1). 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the port as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a one. the port then issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the port discontinues transmission (figure 7-2). 7.3 sequential read sequential reads are initiated in the same way as a random read except that after the port transmits the first data byte, and the master issues an acknowledge as opposed to a stop condition in a random read. this directs the port to transmit the next sequentially addressed 8-bit word (figure 7-3). to provide sequential reads, the port contains an internal address pointer, which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 7.4 noise protection both the ddc monitor port and microcontroller access port employ a v cc threshold detector circuit which disables the internal erase/write logic, if the v cc is below 1.5 volts at nominal conditions. the dscl, mscl, dsda and msda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. figure 7-1: current address read sp bus activity master dsda or bus activity s t a r t control byte data n a c k n o a c k s t o p msda line
24lc41 ds21140f-page 12 ? 2004 microchip technology inc. figure 7-2: random read figure 7-3: sequential read s p s bus activity master msda line bus activity s t a r t s t o p control byte word address data n a c k a c k n o a c k control byte a c k s t a r t p dsda or bus activity s t o p control byte data n a c k n o a c k a c k a c k a c k data n + 1 data n + 2 data n + x bus activity master msda line
? 2004 microchip technology inc. ds21140f-page 13 24lc41 8.0 pin descriptions the descriptions of the pins are listed in table 8-1. table 8-1: pin function table 8.1 dsda this pin is used to transfer addresses and data into and out of the ddc monitor port, when the device is in the bidirectional mode. in the transmit-only mode, which only allows data to be read from the device, data is also transferred on the dsda pin. this pin is an open drain terminal, therefore the dsda bus requires a pull-up resistor to v cc (typical 10k ? for 100 khz, 2 k ? for 400 khz). for normal data transfer in the bidirectional mode, dsda is allowed to change only during dscl or msda low. changes during dscl high are reserved for indicating the start and stop conditions. 8.2 dscl this pin is the clock input for the ddc monitor port while in the bidirectional mode, and is used to synchro- nize data transfer to and from the device. it is also used as the signaling input to switch the device from the transmit-only mode to the bidirectional mode. it must remain high for the chip to continue operation in the transmit-only mode. 8.3 vclk/dwp this pin is the clock input for the ddc monitor port while in the transmit-only mode. in the transmit-only mode, each bit is clocked out on the rising edge of this signal. in the bidirectional mode, a high logic level is required on this pin to enable write capability. 8.4 mscl this pin is the clock input for the microcontroller access port, and is used to synchronize data transfer to and from the device. 8.5 msda this pin is used to transfer addresses and data into and out of the microcontroller access port. this pin is an open drain terminal, therefore the msda bus requires a pull-up resistor to v cc (typical 10k ? for 100 khz, 2k ? for 400 khz). msda is allowed to change only during mscl low. changes during mscl high are reserved for indicating the start and stop conditions. 8.6 mwp this pin is used to write-protect the 4k memory array for the microcontroller access port. this pin must be connected to either v ss or v cc . if tied to vss, normal memory operation is enabled (read/write the entire memory). if tied to v cc , write operations are inhibited. the entire memory will be write-protected. read operations are not affected. name function dscl serial clock for ddc bidirectional mode (ddc2) dsda serial address and data i/o (ddc bus) vclk/dwp serial clock for ddc transmit-only mode (ddc1)/write-protect mscl serial clock for 4 kbit mcu port msda serial address and data i/o for 4 kbit mcu port mwp hardware write-protect for 4 kbit mcu port v ss ground v cc +2.5v to +5.5v power supply
24lc41 ds21140f-page 14 ? 2004 microchip technology inc. appendix a: revision history revision e corrections to section 1.0, electrical characteristics.
? 2004 microchip technology inc. ds21140f-page 15 24lc41 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support part no. x /xx xxx pattern package temperature range device device 24lc41 dual mode, dual port i 2 c serial eeprom temperature range blank = 0 c to +70 c i= -40 c to +85 c package p = pdip data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
24lc41 ds21140f-page 16 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21140f-page 17 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of micr ochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance ar e trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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